Humboldt-Stipendiat Salem

Research Fellow – Facts

Porträt von Dr. Mohamed Abd El Ghany Salem. Bild: Felipe Fernandes
Dr. Mohamed Abd El Ghany Salem. Photo: Felipe Fernandes

Name: Dr. Mohamed Abd El Ghany Salem

Age: 34

Area of research:

  • Network-on-Chip and System-on-Chip
  • High performance VLSI circuits
  • Clock distribution network design
  • Low-voltage Low-power designs
  • Application Specific Integrated Circuits (ASIC) design
  • Design and Implementation of Field Programmable Gate Array (FPGA)
  • Digital Electronics and Digital Systems Design

Name of my University / Research Institute: German University in Cairo (GUC)

Research period at the TU Darmstadt:

1 year

 

Questionnaire to the Research Fellow

My field of research is fascinating. To laymen I would explain it in the following comprehensible manner:

To keep pace with market demand for more performance and functionality in electronic products like mobile phones, digital cameras, computers and digital televisions, manufacturers pack billions of transistors onto a single chip. The trend in the semiconductor industry is expected to continue towards higher operating frequencies and increased transistor density. Under these conditions, there is a desire to create 'System on a Chip' (SoC) ICs; the implementation and integration of multiple computers or entire electronic systems (microcontroller, memory block, timers, peripherals, etc…) on a single chip.

As the number and functionality of IP blocks in the SoC increase, the complexity of its interconnect architectures will also increase. While many research works have been published in high performance SoCs, the system scalability and bandwidth remain to be constrained. NoCs are thus emerging as the best replacement in future interconnect architectures.

My most important success in research to date is…

  • Awarded the prestigious Alexander von Humboldt Foundation Postdoctoral Fellowship Germany, Darmstadt University, 2012-2014
  • I am the author of about 20 papers and two book chapters in the fields of high throughput and low-power NoC design
  • Best Paper Award in IEEE International System-on-Chip Conference, Las Vegas, Nevada, USA, September 2010.
  • One of the best research points for 2009 year in the 4th Annual International Scholar Research Exposition, The Ohio State University, USA
Prof. Klaus Hofmann schaut Dr. Salem bei der Arbeit an einer Maschine zu. Bild: Felipe Fernandes
Prof. Hofmann with Dr. Salem. Photo: Felipe Fernandes

I’ve chosen the TU Darmstadt because of…

  • It is one of the highly ranked German Universities in the field of electrical engineer research.
  • The two teams of TU Darmstadt and GUC have a proven record of successfully conducting cooperative research as evidenced by their previous publications.

If I were a student today, I would try to do the best to have what I have now or maybe more …

With the help of my host in Darmstadt I would like to

  • Provide a unique opportunity in solving fundamental design, implementation and testing problems, engaging researchers from Darmstadt University of Technology (TU Darmstadt) and German University in Cairo (GUC). The dissemination of the research know-how will also include organization of scientific workshops and special sessions at international conferences, publications in scientific journals and international conferences and publication of one reference book.
  • Enhance and strengthen the already existing cooperation between GUC and TU Darmstadt and produce unique interdisciplinary research results that would otherwise be difficult to achieve.
 

Questionnaire for the host

Prof. Klaus Hofmann- Bild: Felipe Fernandes
Prof. Klaus Hofmann. Photo: Felipe Fernandes

Guest of: Prof. Dr.-Ing. Klaus Hofmann

Department: ETiT (FB 18), Integrated Electronic Systems

You appreciate in your guest / your guest favourably impressed you by…

His prior knowledge in this field, getting-things-done attitude, scientific optimism.

You, your team and the TU Darmstadt benefit from your guest’s …

In the field of „System-on-Chip“/“Network-on-Chip“ Dr. Salem is bringing in first hand experience that will enable us to approach the heterogeneous topic of “Interconnect Architectures for high-performance Network-on-Chip/Multiprocessorarchitectures. The IES lab is with its GSNoC-simulator able to predict and simulate the quality of service of NoC-architectures in various aspects. Our goal is to extend the simulator capabilities in this research collaboration and to add more realism in the field of system level interconnect prediction that includes the physical/electrical behavior.